Added some notes to readme
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@ -9,7 +9,7 @@ RX Path
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and we need the comparator match event to trigger the ADC.
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- ADC conversions are triggered externally at each comparator match for Timer1 Channel1
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- ADC runs ins Scan-mode, it samples PA2 first, then PA3
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- DMA2 is set up to for device to memory, with memory increment,
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- DMA2 Stream 0 is set up to for device to memory, with memory increment,
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transfer complete interrupt and double buffering disabled.
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- The HAL requires the DMA transfer instance to take ownership of both buffers,
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for the double buffered mode, to swap to the second buffer immediately,
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@ -26,7 +26,7 @@ RX Path
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- The samples are scaled by 2**10 and turned into an array of 128 complex numbers.
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- A FIR-filter for filtering out the sideband is applied to the array
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- The resulting audio is stored in the output buffer
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- DMA1 is set up to transfer the output buffer into CCR3 of Timer4
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- DMA1 Stream 7 is set up to transfer the output buffer into CCR3 of Timer4
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- Similar to the ADC two buffers are used alternating.
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they are swapped out in the transfer complete interrupt.
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- Timer4 is set up to output PWM on Channel3 on PB8
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@ -57,4 +57,6 @@ TX Path
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-TODO:
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- Extracting the amplitude and dominant frequency
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- Predistorted the amplitudes using a LUT, to compensate for non-linearities of the MOSFETs
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- Setup DMA transfers for I2C and bias PWM
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- Setup DMA transfers for I2C and bias PWM
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- DMA1 - Stream 6 for I2C1 TX
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- DMA1 - Stream 4 for TIM1 CH3
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