diff --git a/Cargo.toml b/Cargo.toml
index 78074d6..9b211bf 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -8,7 +8,7 @@ version = "0.1.0"
 [dependencies]
 cortex-m = "0.6"
 cortex-m-rt = "0.6"
-stm32f1xx-hal = { version = "0.5.3", features = ["stm32f103", "stm32-usbd", "rt"] }
+stm32f1xx-hal = { version = "0.6.1", features = ["stm32f103", "stm32-usbd", "rt"] }
 panic-semihosting = "0.5"
 embedded-hal = "0.2.3"
 rtt-target = {version = "0.2.2", features = ["cortex-m"]}
diff --git a/src/main.rs b/src/main.rs
index 055a1e7..8a5130b 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -7,7 +7,7 @@ extern crate panic_semihosting;
 use cortex_m_rt::entry;
 use embedded_hal::digital::v2::OutputPin;
 use rtt_target::{rprintln, rtt_init_print};
-use stm32f1xx_hal::{delay::Delay, pac, prelude::*};
+use stm32f1xx_hal::{delay::Delay, pac, pac::TIM1, pac::TIM2, prelude::*, rcc::Enable, rcc::Reset};
 
 #[entry]
 fn main() -> ! {
@@ -23,9 +23,16 @@ fn main() -> ! {
     let mut flash = dp.FLASH.constrain();
     let mut rcc = dp.RCC.constrain();
 
+    let clocks = rcc
+        .cfgr
+        .use_hse(8.mhz())
+        .sysclk(48.mhz())
+        .pclk1(24.mhz())
+        .freeze(&mut flash.acr);
+
     // Freeze the configuration of all the clocks in the system and store the frozen frequencies in
     // `clocks`
-    let clocks = rcc.cfgr.freeze(&mut flash.acr);
+    //let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
     // Acquire the GPIOC peripheral
     let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
@@ -34,15 +41,55 @@ fn main() -> ! {
     // in order to configure the port. For pins 0-7, crl should be passed instead.
     let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
 
+    // Setup timers
+    let tim1 = dp.TIM1;
+
+    TIM1::enable(&mut rcc.apb2);
+    TIM1::reset(&mut rcc.apb2);
+
+    // Enable external clocking
+    tim1.smcr.write(|w| {
+        w.etf().no_filter(); // No filter
+        w.etps().div1(); // No divider
+        w.etp().not_inverted(); // on rising edege at ETR pin
+        w.ece().enabled() // mode 2 (use ETR pin)
+    });
+
+    tim1.cr2.write(|w| {
+        w.mms().update() // Trigger output on update/overflow
+    });
+
+    // Counting up to 10^7 should need 24 bits
+    // Clock tim2 by tim1s overflow to make a 32bit timer
+
+    let tim2 = dp.TIM2;
+
+    TIM2::enable(&mut rcc.apb1);
+    TIM2::reset(&mut rcc.apb1);
+
+    tim2.smcr.write(|w| {
+        w.ts().itr0(); // Trigger from internal trigger 0
+        w.sms().ext_clock_mode() // Use trigger as clock
+    });
+
+    tim1.cr1.write(|w| w.cen().enabled());
+    tim2.cr1.write(|w| w.cen().enabled());
+
     let mut delay = Delay::new(cp.SYST, clocks);
 
-    // Blink using the delay function
     loop {
-        rprintln!("blink");
-        led.set_high().unwrap();
-        delay.delay_ms(1000u16);
-        rprintln!("blonk");
-        led.set_low().unwrap();
+        let cnt1 = tim1.cnt.read().bits();
+        let cnt2 = tim2.cnt.read().bits();
+        tim1.cnt.reset();
+        tim2.cnt.reset();
+
+        let sum = cnt2 << 16 | cnt1;
+
+        rprintln!("Counters:");
+        rprintln!("cnt1: {}", cnt1);
+        rprintln!("cnt1: {}", cnt2);
+        rprintln!("sum: {}", sum);
+
         delay.delay_ms(1000u16);
     }
 }