144 lines
3.9 KiB
Rust
144 lines
3.9 KiB
Rust
#![deny(unsafe_code)]
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#![no_std]
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#![no_main]
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extern crate panic_semihosting;
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use cortex_m_rt::entry;
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use embedded_hal::digital::v2::OutputPin;
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use rtt_target::{rprintln, rtt_init_print};
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use stm32f1xx_hal::{delay::Delay, pac, pac::TIM1, pac::TIM2, prelude::*, rcc::Enable, rcc::Reset};
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#[entry]
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fn main() -> ! {
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rtt_init_print!();
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// Get access to the core peripherals from the cortex-m crate
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let cp = cortex_m::Peripherals::take().unwrap();
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// Get access to the device specific peripherals from the peripheral access crate
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let dp = pac::Peripherals::take().unwrap();
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// Take ownership over the raw flash and rcc devices and convert them into the corresponding
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// HAL structs
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let mut flash = dp.FLASH.constrain();
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let mut rcc = dp.RCC.constrain();
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let clocks = rcc
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.cfgr
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.use_hse(8.mhz())
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.sysclk(48.mhz())
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.pclk1(24.mhz())
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.freeze(&mut flash.acr);
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// Freeze the configuration of all the clocks in the system and store the frozen frequencies in
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// `clocks`
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//let clocks = rcc.cfgr.freeze(&mut flash.acr);
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// Acquire the GPIOC peripheral
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let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
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// Configure gpio C pin 13 as a push-pull output. The `crh` register is passed to the function
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// in order to configure the port. For pins 0-7, crl should be passed instead.
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let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
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// Setup timers
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let tim1 = dp.TIM1;
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TIM1::enable(&mut rcc.apb2);
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TIM1::reset(&mut rcc.apb2);
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// Enable external clocking
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tim1.smcr.write(|w| {
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w.etf().no_filter(); // No filter for to 10Mhz clock
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w.etps().div1(); // No divider
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w.etp().not_inverted(); // on rising edege at ETR pin
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w.ece().enabled() // mode 2 (use ETR pin)
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});
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tim1.ccmr1_input().write(|w| {
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w.cc1s().ti1();
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w.ic1f().no_filter()
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//w.ic1psc().bits(0)
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});
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tim1.ccer.write(|w| {
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w.cc1p().set_bit();
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w.cc1e().set_bit()
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});
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tim1.cr2.write(|w| {
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w.mms().update() // Trigger output on update/overflow
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});
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// Counting up to 10^7 should need 24 bits
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// Clock tim2 by tim1s overflow to make a 32bit timer
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let tim2 = dp.TIM2;
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TIM2::enable(&mut rcc.apb1);
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TIM2::reset(&mut rcc.apb1);
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tim2.smcr.write(|w| {
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w.ts().itr0(); // Trigger from internal trigger 0
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w.sms().ext_clock_mode() // Use trigger as clock
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});
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tim2.ccmr1_input().write(|w| {
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w.cc1s().ti1();
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w.ic1f().no_filter()
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//w.ic1psc().bits(0)
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});
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tim2.ccer.write(|w| {
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w.cc1p().set_bit();
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w.cc1e().set_bit()
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});
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tim1.cr1.write(|w| w.cen().enabled());
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tim2.cr1.write(|w| w.cen().enabled());
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let mut delay = Delay::new(cp.SYST, clocks);
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let mut last_ic = 0u32;
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let mut avg = 10f64;
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// Skip the first measurement, it will be garbage
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while !tim1.sr.read().cc1if().bit_is_set() || !tim2.sr.read().cc1if().bit_is_set() {
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delay.delay_ms(10u16);
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}
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let ic1 = tim1.ccr1.read().bits();
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let ic2 = tim2.ccr1.read().bits();
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last_ic = ic2 << 16 | ic1;
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loop {
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while !tim1.sr.read().cc1if().bit_is_set() || !tim2.sr.read().cc1if().bit_is_set() {
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delay.delay_ms(10u16);
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}
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let ic1 = tim1.ccr1.read().bits();
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let ic2 = tim2.ccr1.read().bits();
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let sum_ic = ic2 << 16 | ic1;
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let diff_ic = if sum_ic > last_ic {
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sum_ic - last_ic
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} else {
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u32::MAX - last_ic + sum_ic
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};
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last_ic = sum_ic;
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let freq = (diff_ic as f64) / 1_000_000f64;
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avg = avg * 0.99 + freq * 0.01;
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rprintln!("Counters:");
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rprintln!("ic1: {}", ic1);
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rprintln!("ic2: {}", ic2);
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rprintln!("sum_ic: {}", sum_ic);
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rprintln!("diff_ic: {}", diff_ic);
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rprintln!("freq: {} MHz", freq);
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rprintln!("avg: {} MHz", avg);
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}
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}
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