Playing with dma

.cargo/config

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+[build]
+rustc = "hcl/rustc-wrapper"

.gdb_history

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+s
+s
+s
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+continue
+continue
+continue
+continue
+continue
+continue
+continue
+tbre
+
+quitr
+quit
+s
+s
+s
+s
+s
+s
+tbreak timertest::systick
+continue
+continue
+s
+s
+continue
+continue
+quit
+q
+run
+continue
+run
+continue
+exit
+exit()
+continue
+break systick
+break timertest::systick
+continue
+continue
+continue
+break timertest::systick
+contine
+cont
+s
+s
+s
+s
+s
+s
+s
+s
+s
+s
+s
+s
+n
+n
+print cur
+continue
+cont
+cont
+tbreak timertest::systick
+cont
+cont
+continue
+cont
+cont
+cont
+cont
+s
+n
+s
+cont
+cont
+cont
+cont
+cont
+tbreak main.rs:128
+continue
+n
+cont
+tbreak main.rs:111
+cont
+s
+s
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+cont
+cont
+cont
+cont
+ s
+s
+s
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+s
+s
+s
+n
+n
+n
+n
+n
+n
+n
+n
+n
+n
+n
+n
+break main.rs:115
+cont
+break main.rs:113
+cont
+n
+n
+n
+n
+n
+s
+s
+break main.rs:116
+cont
+cont
+cont
+cont
+run
+cont
+s
+s
+n
+n
+n
+n
+n
+n
+n
+break main.rs:50
+cont
+break main.rs:50
+cont
+s
+s
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+break main.rs:50
+cont
+cont
+cont
+cont
+cont
+cont
+cont
+cont
+cont
+cont
+run
+cont
+cont

.gdbinit

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+target remote :3333
+monitor arm semihosting enable
+load
+tbreak run
+monitor reset halt
+continue
+
+#source .gdbdash

.gitignore

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+/target
+**/*.rs.bk

.gitmodules

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+[submodule "hcl"]
+	path = hcl
+	url = https://git.eno.space/hcl.git

Cargo.lock

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+[[package]]
+name = "hcl"
+version = "0.0.0"
+dependencies = [
+ "platform_def 0.1.0",
+]
+
+[[package]]
+name = "hclnom"
+version = "3.2.1"
+dependencies = [
+ "memchr 1.0.2 (registry+https://github.com/rust-lang/crates.io-index)",
+]
+
+[[package]]
+name = "libc"
+version = "0.2.43"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+
+[[package]]
+name = "memchr"
+version = "1.0.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+dependencies = [
+ "libc 0.2.43 (registry+https://github.com/rust-lang/crates.io-index)",
+]
+
+[[package]]
+name = "platform_def"
+version = "0.1.0"
+dependencies = [
+ "hclnom 3.2.1",
+]
+
+[[package]]
+name = "reflow-firmware"
+version = "0.1.0"
+dependencies = [
+ "hcl 0.0.0",
+]
+
+[metadata]
+"checksum libc 0.2.43 (registry+https://github.com/rust-lang/crates.io-index)" = "76e3a3ef172f1a0b9a9ff0dd1491ae5e6c948b94479a3021819ba7d860c8645d"
+"checksum memchr 1.0.2 (registry+https://github.com/rust-lang/crates.io-index)" = "148fab2e51b4f1cfc66da2a7c32981d1d3c083a803978268bb11fe4b86925e7a"

Cargo.toml

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+[package]
+name = "reflow-firmware"
+version = "0.1.0"
+authors = ["ar3itrary <sebastian@sebastians-site.de>"]
+
+[dependencies]
+hcl = { path = "hcl", features = ["stm32f103:b"] }
+
+
+
+[profile.dev]
+opt-level = 2
+debug = 2
+lto = true
+incremental = false
+
+[profile.release]
+opt-level = 3
+lto = true
+incremental = false

build.rs

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+fn main() {
+	println!("cargo:rustc-env=HCL_FIXUP_ARGS=1");
+}

hcl

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+Subproject commit 001d44d6b9693a9ad3fd6fc8bc44e8dc22ad7149

src/debug.rs

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+
+use hcl::platform::usart;
+use hcl::platform::dma;
+use hcl::platform::PeripheralRef;
+use hcl::platform::Location;
+use hcl::dma::*;
+
+use alloc::vec::Vec;
+
+
+type UsartDRRef<Addr> = PeripheralRef<usart::USARTdr, usart::USART_part_offsets::dr<Addr>>;
+type UsartDMAResult<'a, Addr, Chan> = Result<'a, Vec<u8>, UsartDRRef<Addr>, Chan, SetupError>;
+
+
+pub struct UsartPrinter<'a, Addr, Chan : 'a, ChanAddr> where
+    Addr : hcl::platform::Location,
+    Chan: hcl::dma::PeripheralChannel,
+    ChanAddr: hcl::platform::Location {
+    usart_dr: Option<UsartDRRef<Addr>>,
+    dma_result : Option<UsartDMAResult<'a, Addr, Chan>>,
+
+    dma_channel_idx: u32,
+    dma_channel: PeripheralRef<Chan,ChanAddr>,
+}
+
+impl<'a, Addr, Chan, ChanAddr> UsartPrinter<'a, Addr, Chan, ChanAddr> where
+    Addr : hcl::platform::Location,
+    Chan: hcl::dma::PeripheralChannel,
+    ChanAddr: hcl::platform::Location {
+
+    pub fn init(usart: usart::USARTParts<Addr>,
+            dma_channel_idx: u32,
+            dma_channel: PeripheralRef<Chan,ChanAddr>) -> UsartPrinter<'a, Addr, Chan, ChanAddr> {
+        UsartPrinter {
+            usart_dr: Some(usart.dr),
+            dma_result: None,
+            dma_channel_idx: dma_channel_idx,
+            dma_channel: dma_channel,
+        }
+    }
+
+    pub fn wait_for_completion(&mut self, dma_control: &mut dma::DMA1control) -> () {
+        match self.dma_result.take() {
+            Some(res) => {
+                let dr = match res {
+                    Ok(tx) => {
+                        while !dma_control.transfer_complete(self.dma_channel_idx) {
+                        }
+                        tx.retrieve().1
+                    },
+                    Err((_, sink, _)) => sink
+                };
+                self.usart_dr = Some(dr)
+            }
+            None => {}
+        }
+    }
+
+    pub fn print(&'a mut self, data: Vec<u8>, dma_control: & mut dma::DMA1control) -> () {
+        let dr = match self.usart_dr.take() {
+            Some(dr) => dr,
+            None => {
+                self.wait_for_completion(dma_control);
+                self.usart_dr.take().unwrap()
+            }
+        };
+
+        let foo = &self.dma_channel;
+
+        dma_control.clear_transfer_complete(self.dma_channel_idx);
+        self.dma_result = Some(self.dma_channel.begin_source(data, dr));
+    }
+}

src/main.rs

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+#![no_std]
+#![feature(asm, used, const_fn, naked_functions, alloc, box_syntax)]
+#![no_main]
+#![feature(extern_prelude)]
+
+#[macro_use]
+extern crate hcl;
+
+#[macro_use]
+extern crate alloc;
+
+use core::mem;
+use hcl::platform::gpio;
+use hcl::platform::irq;
+use hcl::platform::rcc;
+use hcl::platform::scs;
+use hcl::platform::timer;
+use hcl::platform::usart;
+use hcl::platform::dma;
+use hcl::dma::*;
+
+mod debug;
+
+use debug::UsartPrinter;
+
+fn configure_clocks(rcc: &mut rcc::RCC) {
+    rcc.clock_control.set_hse_on(true);
+    while !rcc.clock_control.hse_ready() {
+    }
+
+    rcc.clock_config.configure(|c| c
+        .set_pll_multiplier(10)
+        .set_pll_source(rcc::PllSource::HsiDiv2));
+
+    rcc.clock_control.set_pll_on(true);
+    while !rcc.clock_control.pll_ready() {
+    }
+
+    rcc.clock_config.switch_clock_source(rcc::SystemClockSource::Pll);
+}
+
+fn configure_peripherals(rcc: &mut hcl::platform::rcc::RCC,
+                                gpio: &mut gpio::GPIO,
+                                usart: &mut usart::USART) {
+    rcc.apb2_enable.set_gpio_a(true);
+    rcc.apb1_enable.configure(|a| a
+        .set_usart2(true));
+    rcc.ahb_enable.set_dma1(true);
+
+    gpio.configure(|g| g
+        .set_mode(2, gpio::PinMode::Output2MHz)
+        .set_output_config(2, gpio::OutputConfig::AfPushPull)
+        .set_mode(3, gpio::PinMode::Output50MHz)
+        .set_output_config(3, gpio::OutputConfig::AfPushPull)
+        .set_mode(5, gpio::PinMode::Output50MHz)
+        .set_output_config(5, gpio::OutputConfig::PushPull));
+
+    usart.configure(|u| u
+        .set_enabled(true)
+        .set_tx_enabled(true)
+        .set_dma_transmit_enabled(true)
+        .set_baudgen((21, 11))); // 115.2 kbaud
+}
+
+
+
+// allowing inlining into main() breaks the stack, since main() must be naked to set up a process stack.
+#[inline(never)]
+fn run(mut scs: scs::Instance, mut p: hcl::platform::Instance) {
+    configure_clocks(&mut p.rcc);
+    configure_peripherals(&mut p.rcc, &mut p.gpio_a, &mut p.usart2);
+
+    let dma = p.dma1.split();
+
+
+    let mut dma_control = dma.control;
+
+
+    let printer = UsartPrinter::init(p.usart2.split(), 7, dma.channel7);
+
+    for i in 0u32..0xffffffff {
+        let x = format!("> {}\r\n", i).into_bytes();
+
+        priner.print(x);
+    }
+
+}
+
+
+entry_point!(main);
+fn main(scs: scs::Instance, p: hcl::platform::Instance) {
+    declare_thread_stack!(stack, 512);
+
+    unsafe {
+        hcl::set_process_stack(&stack);
+        hcl::use_process_stack(true);
+    }
+
+    run(scs, p);
+}