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sss7modem
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Untested Arduino code for mega328

This commit is contained in:
Sebastian 2016-12-25 21:39:33 +01:00
parent 38e7d7bb1e
commit 8169cdc6bf
3 changed files with 19 additions and 19 deletions
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2
software/Arduino/.clang_complete
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@ -1,5 +1,5 @@
-I../sss7core -I../sss7core
-I/usr/avr/include -I/usr/avr/include
-I./arduino-1.6.13/hardware/arduino/avr/cores/arduino/ -I./arduino-1.6.13/hardware/arduino/avr/cores/arduino/
-D__AVR_ATmega2560__ -D__AVR_ATmega328__
-DF_CPU=16000000 -DF_CPU=16000000

2
software/Arduino/Makefile
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@ -1,4 +1,4 @@
AVRMCU ?= atmega2560 AVRMCU ?= atmega328
F_CPU ?= 16000000 F_CPU ?= 16000000
ISPPORT ?= /dev/ttyUSB0 ISPPORT ?= /dev/ttyUSB0

34
software/Arduino/ardusss7.cpp
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@ -33,31 +33,31 @@ void SSS7Wrapper::getReceived(uint8_t msg[SSS7_PAYLOAD_SIZE]) {
void SSS7Wrapper::setupUart() { void SSS7Wrapper::setupUart() {
UBRR2H = UBRR_VAL >> 8; // Setting baudrate UBRR0H = UBRR_VAL >> 8; // Setting baudrate
UBRR2L = UBRR_VAL & 0xFF; UBRR0L = UBRR_VAL & 0xFF;
UCSR2B = (1 << TXEN2) | (1 << RXEN2); // Enable TX and RX UCSR0B = (1 << TXEN0) | (1 << RXEN0); // Enable TX and RX
UCSR2C = (1 << UCSZ21) | (1 << UCSZ20); // Asynchronous 8N1 UCSR0C = (1 << UCSZ01) | (1 << UCSZ00); // Asynchronous 8N1
// flush UDR // flush UDR
do do
{ {
UDR2; UDR0;
} }
while (UCSR2A & (1 << RXC2)); while (UCSR0A & (1 << RXC0));
// reset tx and rx complete flags // reset tx and rx complete flags
UCSR2A = (1 << RXC2) | (1 << TXC2); UCSR0A = (1 << RXC0) | (1 << TXC0);
UCSR2B |= (1 << TXCIE2) | (1 << RXCIE2); // enable tx and rx interrupts UCSR0B |= (1 << TXCIE0) | (1 << RXCIE0); // enable tx and rx interrupts
} }
void uart_put_byte(uint8_t byte) { void uart_put_byte(uint8_t byte) {
UDR2 = byte; UDR0 = byte;
} }
uint8_t uart_get_byte() { uint8_t uart_get_byte() {
return UDR2; return UDR0;
} }
ISR(USART2_RX_vect) { ISR(USART2_RX_vect) {
@ -70,19 +70,19 @@ ISR(USART2_TX_vect) {
void SSS7Wrapper::setupTimer() { void SSS7Wrapper::setupTimer() {
TCCR4B = 0; TCCR1B = 0;
TCNT4 = 65535 - 16000; //Preload for 16000 ticks to overflow TCNT1 = 65535 - 16000; //Preload for 16000 ticks to overflow
// Take the Timer by force ... // Take the Timer by force ...
TCCR4A = 0; TCCR1A = 0;
TCCR4B = (1 << CS40); // Prescaler 1 TCCR1B = (1 << CS10); // Prescaler 1
TCCR4C = 0; TCCR1C = 0;
TIMSK4 = (1 << TOIE4); TIMSK1 = (1 << TOIE1);
} }
ISR(TIMER4_OVF_vect) { ISR(TIMER4_OVF_vect) {
TCNT4 = 65535 - 16000; //Preload for 16000 ticks to overflow TCNT1 = 65535 - 16000; //Preload for 16000 ticks to overflow
sss7_process_ticks(sss7_timeout_increment); sss7_process_ticks(sss7_timeout_increment);
} }