Crude frequency counting works
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@ -8,7 +8,7 @@ version = "0.1.0"
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[dependencies]
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[dependencies]
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cortex-m = "0.6"
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cortex-m = "0.6"
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cortex-m-rt = "0.6"
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cortex-m-rt = "0.6"
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stm32f1xx-hal = { version = "0.5.3", features = ["stm32f103", "stm32-usbd", "rt"] }
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stm32f1xx-hal = { version = "0.6.1", features = ["stm32f103", "stm32-usbd", "rt"] }
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panic-semihosting = "0.5"
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panic-semihosting = "0.5"
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embedded-hal = "0.2.3"
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embedded-hal = "0.2.3"
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rtt-target = {version = "0.2.2", features = ["cortex-m"]}
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rtt-target = {version = "0.2.2", features = ["cortex-m"]}
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63
src/main.rs
63
src/main.rs
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@ -7,7 +7,7 @@ extern crate panic_semihosting;
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use cortex_m_rt::entry;
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use cortex_m_rt::entry;
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use embedded_hal::digital::v2::OutputPin;
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use embedded_hal::digital::v2::OutputPin;
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use rtt_target::{rprintln, rtt_init_print};
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use rtt_target::{rprintln, rtt_init_print};
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use stm32f1xx_hal::{delay::Delay, pac, prelude::*};
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use stm32f1xx_hal::{delay::Delay, pac, pac::TIM1, pac::TIM2, prelude::*, rcc::Enable, rcc::Reset};
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#[entry]
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#[entry]
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fn main() -> ! {
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fn main() -> ! {
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@ -23,9 +23,16 @@ fn main() -> ! {
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let mut flash = dp.FLASH.constrain();
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let mut flash = dp.FLASH.constrain();
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let mut rcc = dp.RCC.constrain();
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let mut rcc = dp.RCC.constrain();
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let clocks = rcc
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.cfgr
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.use_hse(8.mhz())
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.sysclk(48.mhz())
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.pclk1(24.mhz())
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.freeze(&mut flash.acr);
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// Freeze the configuration of all the clocks in the system and store the frozen frequencies in
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// Freeze the configuration of all the clocks in the system and store the frozen frequencies in
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// `clocks`
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// `clocks`
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let clocks = rcc.cfgr.freeze(&mut flash.acr);
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//let clocks = rcc.cfgr.freeze(&mut flash.acr);
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// Acquire the GPIOC peripheral
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// Acquire the GPIOC peripheral
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let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
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let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
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@ -34,15 +41,55 @@ fn main() -> ! {
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// in order to configure the port. For pins 0-7, crl should be passed instead.
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// in order to configure the port. For pins 0-7, crl should be passed instead.
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let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
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let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
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// Setup timers
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let tim1 = dp.TIM1;
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TIM1::enable(&mut rcc.apb2);
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TIM1::reset(&mut rcc.apb2);
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// Enable external clocking
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tim1.smcr.write(|w| {
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w.etf().no_filter(); // No filter
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w.etps().div1(); // No divider
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w.etp().not_inverted(); // on rising edege at ETR pin
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w.ece().enabled() // mode 2 (use ETR pin)
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});
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tim1.cr2.write(|w| {
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w.mms().update() // Trigger output on update/overflow
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});
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// Counting up to 10^7 should need 24 bits
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// Clock tim2 by tim1s overflow to make a 32bit timer
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let tim2 = dp.TIM2;
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TIM2::enable(&mut rcc.apb1);
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TIM2::reset(&mut rcc.apb1);
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tim2.smcr.write(|w| {
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w.ts().itr0(); // Trigger from internal trigger 0
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w.sms().ext_clock_mode() // Use trigger as clock
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});
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tim1.cr1.write(|w| w.cen().enabled());
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tim2.cr1.write(|w| w.cen().enabled());
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let mut delay = Delay::new(cp.SYST, clocks);
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let mut delay = Delay::new(cp.SYST, clocks);
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// Blink using the delay function
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loop {
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loop {
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rprintln!("blink");
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let cnt1 = tim1.cnt.read().bits();
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led.set_high().unwrap();
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let cnt2 = tim2.cnt.read().bits();
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delay.delay_ms(1000u16);
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tim1.cnt.reset();
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rprintln!("blonk");
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tim2.cnt.reset();
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led.set_low().unwrap();
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let sum = cnt2 << 16 | cnt1;
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rprintln!("Counters:");
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rprintln!("cnt1: {}", cnt1);
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rprintln!("cnt1: {}", cnt2);
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rprintln!("sum: {}", sum);
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delay.delay_ms(1000u16);
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delay.delay_ms(1000u16);
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}
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}
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}
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}
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